The present invention relates to a chip design, and more particularly, to a wafer-level package having one die with its clock source shared by multiple dies and an associated clock generating method.
When there are multiple dies assembled in the same package, an accumulated clock phase drift may occur between clocks in two dies. For example, the accumulated clock phase drift has an accumulated time interval error between clocks in two dies, and the accumulated time interval error may result from several factors including process variation, operating condition difference, power noise, etc. When the accumulated clock phase drift occurs, the timing of a clock in one die is not synchronous to the timing of a clock in another die. When setup/hold time violations are caused by the accumulated clock phase drift, the data transfer loss occurs between the two dies. Thus, there is a need for an innovative integrated circuit design which is capable of avoiding data transfer loss resulting from the accumulated clock phase drift of clocks in two dies assembled in the same package.